Title :
Optimizing designs using the addition of deflection operations
Author :
Wong, Jennifer L. ; Potkonjak, Miodrag ; Dey, Sujit
Author_Institution :
Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA
Abstract :
This paper introduces hot potato behavioral synthesis transformation techniques. These techniques add deflection operations in the behavioral description of a computation in such a way that the requirements for two important components of the final implementation cost, the number of registers and the number of interconnects, are significantly reduced. Moreover, we demonstrate how hot potato techniques can be effectively used during behavioral synthesis to minimize the partial scan overhead to make the synthesized design testable.
Keywords :
design for testability; logic design; optimisation; behavioral synthesis transformation techniques; computation behavioral description; deflection operations; design optimization; digital system testing; high-level synthesis; hot potato techniques; implementation cost; interconnect number reduction; partial scan overhead minimization; register number; sequential logic circuit; Circuit synthesis; Computational modeling; Control system synthesis; Costs; Delay; Design optimization; Integrated circuit interconnections; Registers; Testing; Throughput;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2003.819894
