• DocumentCode
    851842
  • Title

    Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique

  • Author

    Alpert, Charles ; Chu, Chris ; Gandham, Gopal ; Hrkic, Milos ; Hu, Jiang ; Kashyap, Chandramouli ; Quay, Stephen

  • Author_Institution
    IBM Corp., Austin, TX, USA
  • Volume
    23
  • Issue
    1
  • fYear
    2004
  • Firstpage
    136
  • Lastpage
    141
  • Abstract
    To achieve timing closure in a placed design, buffer insertion and driver sizing are two of the most effective transforms that can be applied. Since the driver-sizing solution and the buffer-insertion solution affect each other, suboptimal solutions may result if these techniques are applied sequentially instead of simultaneously. We show how to simply extend van Ginneken´s buffer-insertion algorithm to simultaneously incorporate driver sizing and introduce the idea of a delay penalty to encapsulate the effect of driver sizing on the previous stage. The delay penalty can be precomputed efficiently via dynamic programming. Experimental results show that using driver sizing with a delay-penalty function obtains designs with superior timing and area characteristics.
  • Keywords
    buffer circuits; circuit optimisation; driver circuits; dynamic programming; integrated circuit interconnections; integrated circuit layout; timing; delay penalty estimation technique; driver sizing; dynamic programming; interconnection optimization; performance optimization; physical synthesis optimization; simultaneous sizing/insertion; timing closure; van Ginneken buffer-insertion algorithm; Computer science; Delay effects; Delay estimation; Dynamic programming; Heuristic algorithms; Integrated circuit interconnections; Libraries; Optimization; Timing; Wire;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2003.819910
  • Filename
    1256063