A Unibus Processor Interface for a FASTBUS Data Acquisition System

Current work on a FASTBUS data acquisition system at Fermilab is described. The system will consist of three pieces of FASTBUS hardware: a UNIBUS processor interface (UPI), a dual-ported bulk memory, and a FASTBUS "event builder" (i.e., data acquisition processor). Our primary efforts have been on specifying and constructing a UPI. The present specification includes capability for all basic FASTBUS operations, including list processing of consecutive FASTBUS operations. In addition, the UPI will accept FASTBUS interrupts, allow UNIBUS DMA devices to access FASTBUS memory, and allow protected access to UNIBUS memory by FASTBUS devices. Some possible FASTBUS data acquisition system architectures employing the UPI will be discussed along with some detailed specifications of the UPI itself.