Title :
A fault-tolerant systolic sorter
Author :
Choi, Yoon-Hwa ; Malek, Miroslaw
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
fDate :
5/1/1988 12:00:00 AM
Abstract :
A fault-tolerant systolic sorter design is proposed. An algorithm-based fault tolerance is achieved by testing the invariants of a systolic sorter during normal operation. Transient and permanent computation errors can be detected by using error-checking code and some redundant cells. A block with a single faulty cell can be located. Small hardware overhead and negligible time overhead are shown to be the major advantages of the method. A hierarchical structure is suggested as an efficient architecture for realizing the method. An offline fault-testing method for permanent stuck-at faults is presented
Keywords :
automatic testing; cellular arrays; digital integrated circuits; error detection codes; fault tolerant computing; integrated circuit testing; redundancy; sorting; VLSI sorter; algorithm-based fault tolerance; error-checking code; fault-tolerant systolic sorter; hardware overhead; invariants; offline fault-testing; permanent computation errors; permanent stuck-at faults; reconfiguration; redundant cells; single faulty cell; testing; time overhead; Circuit faults; Computer architecture; Degradation; Fault diagnosis; Fault tolerance; Particle separators; Signal processing algorithms; Systolic arrays; Testing; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on