DocumentCode :
852916
Title :
Watermarking graph partitioning solutions
Author :
Wolfe, Greg ; Wong, Jennifer L. ; Potkonjak, Miodrag
Author_Institution :
California Univ., Los Angeles, CA, USA
Volume :
21
Issue :
10
fYear :
2002
fDate :
10/1/2002 12:00:00 AM
Firstpage :
1196
Lastpage :
1204
Abstract :
The authors introduce an Intellectual Property Protection (IPP) technique for graph partitioning which watermarks solutions to the graph partitioning problems so that they carry an author´s signature. This technique is completely transparent to the actual computer-aided design tool which does the partitioning and is implemented by preprocessing and postprocessing alone. The authors propose five different schemes for the watermarking of partitioning solutions. The goal is to construct a partitioning solution which not only has a small edge cut, but also encodes the signature of the author. The key idea of all of our schemes is to map the signature into a set of constraints and then satisfy a disproportionate number of these constraints. Four of our schemes are based upon the idea of encouraging groups of vertices to be in the same partition. The fifth is based upon the encouragement of certain edges to be cut by the partitioning. The fifth scheme shows superior performances on all of the cases which we tested, including both two-way and multiway partitioning. The watermarking scheme produces solutions that have very low-quality degradation levels, yet carry signatures that are convincingly unambiguous, extremely unlikely to be present by coincidence and difficult to detect or remove without completely resolving the partitioning problem.
Keywords :
VLSI; circuit optimisation; copy protection; industrial property; logic CAD; logic partitioning; NP-complete; VLSI design; computer-aided design; generic forensic engineering approach; graph partitioning; groups of vertices; intellectual property protection technique; low-quality degradation levels; multiway partitioning; objective function modification; optimization problem; partitioning heuristics; postprocessing; preprocessing; set of constraints; two-way partitioning; Degradation; Design automation; Helium; Intellectual property; Performance evaluation; Process design; Protection; Testing; Very large scale integration; Watermarking;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2002.802277
Filename :
1043902
Link To Document :
بازگشت