Title :
Low-Threshold-Voltage TaN/Ir/LaTiO p-MOSFETs Incorporating Low-Temperature-Formed Shallow Junctions
Author :
Lin, S.H. ; Cheng, C.H. ; Chen, W.B. ; Yeh, F.S. ; Chin, Albert
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu
fDate :
6/1/2009 12:00:00 AM
Abstract :
We demonstrate a low threshold voltage (Vt) of -0.17 V and good hole mobility (54 cm2/V middot s at 0.8 MV/cm) in TaN/Ir/LaTiO p-MOSFETs at an equivalent oxide thickness of only 0.66 nm. This was achieved by using Ni-induced solid-phase diffusion of SiO2-covered Ni/Ga which reduced the high-kappa dielectric interfacial reactions. This approach, along with its self-aligned and gate-first process, is compatible with current VLSI technology.
Keywords :
MOSFET; VLSI; Ni-induced solid-phase diffusion; TaN-Ir-LaTiO; VLSI technology; equivalent oxide thickness; gate-first process; good hole mobility; high-kappa dielectric interfacial reaction; low threshold voltage; low-temperature-formed shallow junction; low-threshold-voltage p-MOSFET; self-aligned process; LaTiO; low $V_{t}$; solid-phase diffusion (SPD);
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2009.2020307
