• DocumentCode
    856056
  • Title

    Energy-Efficient Thread-Level Speculation

  • Author

    Renau, Jose ; Strauss, Karin ; Ceze, Luis ; Liu, Wei ; Sarangi, Smruti R. ; Tuck, James ; Torrellas, Josep

  • Author_Institution
    California Univ., Santa Cruz, CA
  • Volume
    26
  • Issue
    1
  • fYear
    2006
  • Firstpage
    80
  • Lastpage
    91
  • Abstract
    Chip multiprocessors with thread-level speculation have become the subject of intense research, this article refutes the claim that such a design is necessarily too energy inefficient. In addition, it proposes out-of-order task spawning to exploit more sources of speculative task-level parallelism
  • Keywords
    microprocessor chips; multi-threading; multiprocessing systems; power consumption; chip multiprocessors; energy-efficient thread-level speculation; out-of-order task spawning; speculative task-level parallelism; Design optimization; Energy consumption; Energy efficiency; Engines; Hardware; Microarchitecture; Out of order; Parallel processing; Process design; Runtime; Thread-level speculation; chip multiprocessors; out-of-order task spawning;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2006.11
  • Filename
    1603500
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=856056