A cost-effective approach to the design and layout of a 14-b current-steering DAC macrocell

Author

Starzyk, Janusz A. ; Mohn, Russell P. ; Jing, Liang

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Ohio Univ., Columbus, OH, USA

Volume

51

Issue

1

fYear

2004

Firstpage

196

Lastpage

200

Abstract

This brief discusses the economical design of a 14-b current-steering digital-to-analog converter (DAC) macrocell for integration with other analog and digital macrocells in a system-on-chip (SOC). The DAC design is targeted for a standard 0.13-μm six-metal single-poly CMOS process. A novel algorithm sets the switching order of individual current sources and minimizes systematic mismatch errors. The design approach minimizes total fabrication cost of the SOC without a loss to specified DAC design requirements. Total macrocell design area is 2.9 mm².

Keywords

CMOS integrated circuits; cellular arrays; digital-analogue conversion; integrated circuit layout; mixed analogue-digital integrated circuits; system-on-chip; INL design specification; cost-effective approach; current source matching; current-steering DAC macrocell; economical design; good die yield; macrocell layout; mixed-signal system-on-chip; six-metal single-poly CMOS process; switching order; systematic mismatch errors; CMOS process; Costs; Digital-analog conversion; Dynamic range; Fabrication; Linearity; Macrocell networks; Process design; System-on-a-chip; Temperature;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2003.821282

Filename

1259504