A 9-b 40-MSample/s reconfigurable pipeline analog-to-digital converter

In this paper, a reconfigurable pipeline analog-to-digital converter (ADC) architecture is proposed. Based on dynamic performance measurements, the best performance configuration will be chosen from a collection of possible configurations. A 40-MSample/s 9-b reconfigurable pipeline ADC is designed and implemented in Taiwan Semiconductor Manufacturing Corporation´s (TSMC´s) 0.25-μm single-poly CMOS digital process. The chip is measured for all the configurations under different temperatures to prove the reconfiguration will provide significant effective number of bits (ENOB) improvement among the set of configurations. The active area of the design is 5.9 mm². The power consumption is 425 mW.