Title :
A low power VLSI architecture for mesh-based video motion tracking
Author :
Badawy, Wael ; Bayoumi, Magdy A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada
fDate :
7/1/2002 12:00:00 AM
Abstract :
This paper proposes a low-power very large-scale integration (VLSI) architecture for motion tracking. It uses a hierarchical adaptive structured mesh that generates a content-based video representation. The proposed mesh is a coarse-to-fine hierarchical two-dimensional mesh that is formed by recursive triangulation of the initial coarse mesh geometry. The structured mesh offers a significant reduction in the number of bits that describe the mesh topology. The motion of the mesh nodes represents the deformation of the video object. The architecture consists of motion estimation and motion compensation units. The motion estimation architecture generates a progressive mesh code and the motion vectors of the mesh nodes. It reduces the power consumption, uses a simpler approach for mesh construction, approximates the mesh nodes motion vector by using the three step search algorithm and uses a parallel motion estimation core to evaluate the mesh nodes motion vectors. Moreover, it maximizes the lifetime of the internal buffers. The motion compensation architecture uses a multiplication-free algorithm for affine transformation, which significantly reduces the complexity of the motion compensation architecture. Moreover, using pipelined affine units contributes to the power savings. The video motion compensation architecture processes a reference frame, mesh nodes and motion vectors to predict a video frame. It implements parallel threads in which each thread implements a pipelined chain of scalable affine units. This motion compensation algorithm allows the use of one simple warping unit to map a hierarchical structure. The affine unit warps the texture of a patch at any level of hierarchical mesh independently. The processor uses a memory serialization unit, which interfaces the memory to the parallel units. The architecture has been prototyped using top-down low-power design methodology. The performance analysis shows that this processor can be used in online object-based video applications such as in MPEG and VRML.
Keywords :
CMOS digital integrated circuits; digital signal processing chips; image representation; image sequences; low-power electronics; mesh generation; motion compensation; motion estimation; pipeline processing; video coding; video signal processing; CMOS VLSI circuits; MPEG; VRML; affine transformation; coarse-to-fine hierarchical two-dimensional mesh; content-based video representation; hierarchical adaptive structured mesh; internal buffer lifetime; low power VLSI architecture; memory serialization unit; mesh construction; mesh node motion; mesh topology; mesh-based video motion tracking; motion compensation architecture; motion estimation architecture; motion vectors; multiplication-free algorithm; online object-based video applications; parallel motion estimation core; parallel threads; patch texture warping; performance analysis; pipelined affine units; power consumption; progressive mesh code; recursive triangulation; reference frame processing; three step search algorithm; top-down low-power design methodology; video frame; video object deformation; warping unit; Energy consumption; Geometry; Large scale integration; Mesh generation; Motion compensation; Motion estimation; Topology; Tracking; Very large scale integration; Yarn;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
DOI :
10.1109/TCSII.2002.805248