Title :
A fully bypassed six-issue integer datapath and register file on the Itanium-2 microprocessor
Author :
Fetzer, Eric S. ; Gibson, Mark ; Klein, Anthony ; Calick, Naomi ; Zhu, Chengyu ; Busta, Eric ; Mohammad, Baker
Author_Institution :
Hewlett-Packard Co., Fort Collins, CO, USA
fDate :
11/1/2002 12:00:00 AM
Abstract :
The six-issue integer datapath of the second-generation Itanium microprocessor is described. Pulse techniques enable a high-speed, 20-ported, 128-entry, 65 bit register file with only 12 wordlines per register. A four-stage operand bypass network achieves a fully bypassed design with operands sourced from 34 locations with 16 destinations. To control this network, over 280 bypass comparators are utilized. Using half a clock for execution and half a clock for bypass, each result is available for the next instruction. Functional units are pre-enabled, reducing power consumption by 15% while eliminating a stage of result mixing and improving performance. The part is fabricated in a six-layer 0.18 μm process and operates at 1.0 GHz at 1.5 V, consuming less than 130 W in about 420 mm2.
Keywords :
CMOS digital integrated circuits; VLSI; integrated circuit noise; microprocessor chips; timing; very high speed integrated circuits; 0.18 micron; 1 GHz; 1.5 V; 130 W; 64 bit; 65 bit; Itanium-2 microprocessor; bypass comparators; four-stage operand bypass network; fully bypassed six-issue integer datapath; high-speed register file; power consumption reduction; pulse techniques; six-issue integer datapath; six-layer CMOS process; Clocks; Decoding; Energy consumption; Integrated circuit noise; Integrated circuit synthesis; Microprocessors; Radio frequency; Registers; Timing; Wire;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2002.803948
