Title :
A 125-mm2 1-Gb NAND flash memory with 10-MByte/s program speed
Author :
Imamiya, Kenichi ; Nakamura, Hiroshi ; Himeno, Toshihiko ; Yarnamura, T. ; Ikehashi, Tamio ; Takeuchi, Ken ; Kanda, Kazushige ; Hosono, Koji ; Futatsuyama, Takuya ; Kawai, Koichi ; Shirota, Riichiro ; Arai, Norihisa ; Arai, Fumitaka ; Hatakeyama, Kazuo ;
Author_Institution :
Toshiba Corp., Kanagawa, Japan
fDate :
11/1/2002 12:00:00 AM
Abstract :
A single 3-V only, 1-Gb NAND flash memory has been successfully developed. The chip has been fabricated using 0.13-μm CMOS STI technology. The effective cell size including the select transistors is 0.077 μm2. To decrease the chip size, a new architecture is introduced. The in-series connected memory cells are increased from 16 to 32. Furthermore, as many as 16 k memory cells are connected to the same wordline. As a result, the chip size is decreased by 15%. A very small die size of 125 mm2 and an excellent cell area efficiency of 70% are achieved. As for the performance, a very fast programming and serial read are realized. The highest program throughput ever of 10.6-MByte/s is realized: 1) by quadrupling the page size and 2) by newly introducing a write cache. In addition, the garbage collection is accelerated to 9.4-MByte/s. In addition, the write cache accelerates the serial read operation and a very fast 20-MByte/s read throughput is realized.
Keywords :
CMOS memory circuits; NAND circuits; PLD programming; cache storage; flash memories; memory architecture; 0.13 micron; 1 Gbit; 10 MByte/s; 20 MByte/s; 3 V; 9.4 MByte/s; CMOS STI technology; NAND flash memory; fast programming; fast serial read operation; garbage collection accelerated; in-series connected memory cells; memory architecture; program throughput; write cache; Acceleration; CMOS technology; Costs; Digital audio players; Digital cameras; Flash memory; Helium; Sun; Throughput; Wiring;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2002.802355
