High-performance 1-Gb-NAND flash memory with 0.12-μm technology

Author

Lee, June ; Im, Heung-Soo ; Byeon, Dae-Seok ; Lee, Kyeong-Han ; Chae, Dong-Hyuk ; Lee, Kyong-Hwa ; Hwang, Sang Won ; Lee, Sung-Soo ; Lim, Young-Ho ; Lee, Jae-Duk ; Choi, Jung-Dal ; Seo, Young-Il ; Lee, Jong-Sik ; Suh, Kang-Deog

Author_Institution

Memory Div., Samsung Electron., Kyunggi, South Korea

Volume

37

Issue

11

fYear

2002

fDate

11/1/2002 12:00:00 AM

Firstpage

1502

Lastpage

1509

Abstract

A 1.8-V, 1-Gb NAND flash memory is fabricated with 0.12-μm CMOS STI process technology. For higher integration, a 32-cell NAND structure, which enables row decoder layout in one block pitch, is applied for the first time. Resulting cell and die sizes are 0.076 μm² and 129.6 mm², respectively. A pseudo-4-phase charge pump circuit can generate up to 20 V even under the supply voltage of 1.6 V. A newly applied cache program function and expanded page size of (2 k + 64) byte lead to program throughput of 7 MB/s. The page copy-back function is provided for on-chip garbage collection. The read throughput of 27 MB/s is achieved by simply expanding I/O width and page size. A measured disturbance free-window of 3.5 V at 1.5 V-V_DD is obtained.

Keywords

CMOS memory circuits; NAND circuits; cache storage; flash memories; 0.12 micron; 1 Gbit; 1.5 to 1.8 V; 20 V; 27 MB/s; 32-cell NAND structure; 7 MB/s; CMOS STI process technology; CMOS memory circuits; NAND flash memory; cache program function; expanded page size; high-performance flash memory; on-chip garbage collection; page copy-back function; program throughput; pseudo-4-phase charge pump circuit; row decoder layout; CMOS memory circuits; CMOS process; CMOS technology; Charge pumps; Decoding; Image storage; Integrated circuit measurements; Nonvolatile memory; Throughput; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.802352

Filename

1046095