The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor

Author

Weiss, Don ; Wuu, John J. ; Chin, Victor

Author_Institution

Hewlett-Packard Co., Fort Collins, CO, USA

Volume

37

Issue

11

fYear

2002

fDate

11/1/2002 12:00:00 AM

Firstpage

1523

Lastpage

1529

Abstract

The 3-MB on-chip level three cache in the Itanium 2 processor, built on an 0.18-μm, six-layer Al metal process, employs a subarray design style that efficiently utilizes available area and flexibly adapts to floor plan changes. Through a distributed decoding scheme and compact circuit design and layout, 85% array efficiency was achieved for the subarrays. In addition, various test and reliability features were included. The cache allows for a store and a load every four core cycles and has been characterized to operate above 1.2 GHz at 1.5 V and 110°C. When running at 1.0 GHz, the cache provides a total bandwidth of 64 GB/s.

Keywords

CMOS digital integrated circuits; CMOS memory circuits; cache storage; integrated circuit reliability; memory architecture; microprocessor chips; random-access storage; timing; 0.18 micron; 1.2 GHz; 1.5 V; 110 degC; 3 MB; Al; Itanium 2 microprocessor; RAM; compact circuit design; compact layout; distributed decoding scheme; floorplan changes; memory architectures; on-chip cache; random-access memories; reliability features; six-layer Al metal process; subarray-based third-level cache; test features; Bandwidth; Circuit synthesis; Circuit testing; Costs; Decoding; Delay; Memory architecture; Microprocessors; Shape; System buses;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.802354

Filename

1046097