DocumentCode
860273
Title
Analysis of a double-latch synchroniser circuit
Author
Jackson, T.A. ; Albicki, A.
Author_Institution
Dept. of Electr. Eng., Rochester Univ., NY, USA
Volume
25
Issue
5
fYear
1989
fDate
3/2/1989 12:00:00 AM
Firstpage
315
Lastpage
316
Abstract
A model for a synchroniser composed of two serially connected D-latches is constructed and analysed to determine the mean time between failures. The analysis demonstrates that the best synchroniser reliability is obtained using a single-latch synchroniser.
Keywords
flip-flops; sequential circuits; double-latch synchroniser circuit; mean time between failures; serially connected D-latches; single-latch synchroniser; synchroniser reliability;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19890219
Filename
19737
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