Title :
Analysis of a double-latch synchroniser circuit
Author :
Jackson, T.A. ; Albicki, A.
Author_Institution :
Dept. of Electr. Eng., Rochester Univ., NY, USA
fDate :
3/2/1989 12:00:00 AM
Abstract :
A model for a synchroniser composed of two serially connected D-latches is constructed and analysed to determine the mean time between failures. The analysis demonstrates that the best synchroniser reliability is obtained using a single-latch synchroniser.
Keywords :
flip-flops; sequential circuits; double-latch synchroniser circuit; mean time between failures; serially connected D-latches; single-latch synchroniser; synchroniser reliability;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19890219
