DocumentCode :
860650
Title :
1.2V and 8.6mW CMOS differential receiver front-end with 24 dB gain and -11dBm IRCP
Author :
Huang, D. ; Wong, R. ; Chien, C. ; Chang, M.-C.F.
Author_Institution :
Dept. of Electr. Eng., Univ. of California, CA
Volume :
42
Issue :
25
fYear :
2006
Firstpage :
1449
Lastpage :
1450
Abstract :
A 60 GHz CMOS differential receiver front-end has been demonstrated by using a novel transformer-folded-cascade (Origami) circuit architecture with high gain (24 dB without buffer amplifier), high linearity (-11 dBm input referred P1 dB compression point, or IRCP), low power dissipation (4.3 mW/arm) and small die area (0.022 mm2)
Keywords :
CMOS analogue integrated circuits; low-power electronics; millimetre wave receivers; radio receivers; 1.2 V; 24 dB; 60 GHz; 8.6 mW; CMOS differential receiver front-end; IRCP; transformer folded cascade circuit architecture;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:20063368
Filename :
4030671
Link To Document :
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