Event-driven incremental timing fault simulator

Author

Jou, S.-J. ; Chiou, S.-H. ; Tao, Y.-S. ; Shen, W.-Z.

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., China

Volume

140

Issue

1

fYear

1993

fDate

2/1/1993 12:00:00 AM

Firstpage

45

Lastpage

54

Abstract

In this paper, FMOTA, an efficient simulator of multiple sets of multiple faults, with electrical timing information for an MOS IC, is presented. The physical faults in a real circuit are modelled more realistically by the node-short, line-open and threshold voltage degradation faults at the transistor level. On using event-driven, selective trace and mixed incremental-in-space, signal and time simulation techniques, the simulation results show that it is superior to other approaches in speed, extra memory used, and precision. Moreover, this simulator is suitable for parallel simulation in a multiprocessor system

Keywords

MOS integrated circuits; VLSI; circuit analysis computing; digital simulation; failure analysis; fault location; integrated logic circuits; logic CAD; parallel algorithms; FMOTA; MOS IC; electrical timing information; incremental timing fault simulator; line-open; multiple faults; multiprocessor system; node-short; parallel simulation; physical faults; threshold voltage degradation faults;

fLanguage

English

Journal_Title

Circuits, Devices and Systems, IEE Proceedings G

Publisher

iet

ISSN

0956-3768

Type

jour

Filename

197474