DocumentCode
860941
Title
The impact of device scaling and power supply change on CMOS gate performance
Author
Chen, Kai ; Wann ; Ko, Ping K. ; Hu, Chenming
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Volume
17
Issue
5
fYear
1996
fDate
5/1/1996 12:00:00 AM
Firstpage
202
Lastpage
204
Abstract
Based a new empirical mobility model that is solely dependent on V/sub gs/, V/sub t/, and T/sub ox/ and a corresponding saturation drain current (I/sub dsat/) model, the impact of device scaling and power supply voltage change on CMOS inverter´s performance is investigated in this paper. It shows that the T/sub ox/ which maximizes inverter´s speed may be thicker than reliability consideration requires. In addition, very high speed can be achieved even at low V/sub dd/ (for low power applications) if V/sub t/ can be lowered.
Keywords
CMOS logic circuits; carrier mobility; integrated circuit modelling; logic gates; CMOS gate performance; CMOS inverter; device scaling; empirical mobility model; high speed operation; power supply change; saturation drain current model; Capacitance; Charge carrier processes; Degradation; Electron mobility; Inverters; MOS devices; MOSFET circuits; Power supplies; Semiconductor device modeling; Voltage;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.491829
Filename
491829
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