DocumentCode :
861001
Title :
High-speed division unit using asymmetric neural network architecture
Author :
Huang, H. ; Siy, P.
Author_Institution :
Dept. of Electr. & Comput. Eng., Wayne State Univ., Detroit, MI, USA
Volume :
25
Issue :
5
fYear :
1989
fDate :
3/2/1989 12:00:00 AM
Firstpage :
344
Lastpage :
345
Abstract :
A neural network with symmetric synaptic connections has been shown to be an effective computational unit. However, this model does not always guarantee global convergence nor yield a fast settling time. An asymmetric model without these problems is introduced and a high-speed divider illustrates its computational capabilities.
Keywords :
analogue computer circuits; dividing circuits; neural nets; parallel architectures; analogue computation; asymmetric neural network architecture; computational unit; fast settling time; global convergence; high-speed divider; symmetric synaptic connections;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19890239
Filename :
19757
Link To Document :
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