Performance of MVTL logic at multi-GHz frequencies

Demonstrating superconductive logic circuits at high speeds is crucial in gaining acceptance by potential users. We are taking an integrated approach toward demonstrating the potential of such circuits. Issues addressed include the effects that layout have upon a circuit and gate (particularly in scaling down the size of gates to increase density), testing limitations, designing for minimum crosstalk and ground ripple, and fundamental limitations to gate performance. In this paper, we report our progress in resolving and understanding these issues. Circuits such as shift registers were used to understand the influence of layout on performance, circuits such as gate chains and punchthrough detectors to explore fundamental gate limitations. We also report on signal processing circuits of several hundred gates tested at clock frequencies up to several hundred MHz and the relationship between these results and the fundamental gate performances.<>