Title :
Hybrid Josephson-CMOS FIFO
Author :
Feldman, A.R. ; Van Duzer, T.
Author_Institution :
Dept. of Electr. Eng., California Univ., Berkeley, CA, USA
fDate :
6/1/1995 12:00:00 AM
Abstract :
We describe the design of a hybrid Josephson-CMOS first-in-first-out memory (FIFO) for communications and signal processing applications. The FIFO takes advantage of high speed Josephson logic and dense CMOS memory. We focus on the low power CMOS ring pointer architecture employing a dual-port CMOS SRAM array and illustrate how a high speed Josephson demultiplexor-multiplexor pair can greatly increase throughput. We describe a novel eight transistor dual-port CMOS SRAM cell with low swing write and current-mode read with an asymmetric SQUID to perform differential current-sensing. Finally, we discuss the peripheral Josephson demultiplexor and multiplexor designed in edge-triggered logic.<>
Keywords :
CMOS memory circuits; SRAM chips; demultiplexing equipment; integrated circuit design; memory architecture; multiplexing equipment; superconducting logic circuits; 5 GHz; asymmetric SQUID; current-mode read; dense CMOS memory; differential current-sensing; dual-port CMOS SRAM array; edge-triggered logic; eight transistor dual-port CMOS SRAM cell; high speed Josephson demultiplexor-multiplexor pair; high speed Josephson logic; hybrid Josephson-CMOS FIFO memory; low power CMOS ring pointer architecture; low swing write; peripheral Josephson demultiplexor; peripheral Josephson multiplexor; signal processing applications; throughput; CMOS logic circuits; CMOS technology; Clocks; Josephson junctions; Random access memory; SQUIDs; Shift registers; Synchronization; Throughput; Timing;
Journal_Title :
Applied Superconductivity, IEEE Transactions on
