Design and implementation of a novel sync processing system for composite video signals

Sync processing will continue to be a mandatory block for future fully digital multimedia terminals, to offer a compatible analog video input. Conventional sync processing circuits employ a sync slicer combined with a PLL (phase locked loop) for line frequency filtering. The PLL is used for historical reasons and for ease of implementation, which however fundamentally limits the performance. This paper presents the prototype realization of a novel sync processing system, which offers a performance that is impossible with PLL-based solutions. It avoids any recursive processing blocks, is based on a free running clock system, and still delivers an orthogonal output pixel pattern. This paper concentrates on the prototypical implementation on a FPGA board and a synthesized design on a 0.35 μm CMOS technology. Compared with state of the art PLL technology, the FGPA prototype demonstrates impressively the improved picture stability with all sources, especially with noisy and unstable analog signals.