New Developments in Segment Ancillary Logic for FASTBUS

Segment Ancillary Logic hardware for FASTBUS systems provides logical functions required in common by all devices attached to a segment. It controls the execution of arbitration cycles, and geographical address cycles, and generates the system handshake responses for broadcast operations. The mandatory requirements for Segment Ancillary Logic in the FASTBUS specifications are reviewed. A detailed implementation based on ECL logic is described, and the hardware to be used on an ECL cable segment for an experimental FASTBUS system at SLAC is shown.