DocumentCode
863038
Title
An I/O Register to FASTBUS Interface
Author
Logg, C.A. ; Paffrath, L.
Author_Institution
Electronics Department Stanford Linear Accelerator Center Stanford University, Stanford, California 94305
Volume
30
Issue
1
fYear
1983
Firstpage
228
Lastpage
231
Abstract
An input/output register to FASTBUS interface (IORFI) has been designed which provides an inexpensive and simple means to connect a computer to a FASTBUS backplane segment. The FASTBUS backplane interface is built on a single width FASTBUS module. It is connected to a computer by two 16-bit parallel input registers and two 16-bit parallel output registers, which makes the interface computer-non-specific. This paper describes the operational characteristics of this interface, its advantages, limitations, and briefly, the uses to which it has been put.
Keywords
Backplanes; Computer interfaces; Concurrent computing; Fastbus; Linear accelerators; Protocols; Prototypes; Registers; Signal generators; Timing;
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/TNS.1983.4332260
Filename
4332260
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