Properties of passive structures for multilayer HTS digital circuits

The passive structures required for HTS digital circuits that must be formed at high temperature (650-750/spl deg/C) were evaluated by fabricating crossovers, vias, YBCO/YBCO contacts, and multiple coverage of steps with trilayer structures of YBCO/epitaxial insulator/YBCO. Two insulator materials were used, high-/spl epsiv/ SrTiO/sub 3/ and relatively low-/spl epsiv/ Sr/sub 2/AlTaO/sub 6/ (SAT). The deposition conditions for both insulators had to be optimized to simultaneously obtain smooth surfaces, sufficiently high oxygen diffusion rates to re-oxidize underlying YBCO, and resistivities in planar capacitor structures of >10/sup 9/ /spl Omega/-cm at 77 K. The particular process used to clean film surfaces after photolithography and Ar ion milling was also critical in obtaining smooth surfaces for a subsequently deposited film layer. For the non-planar capacitor structures formed at crossovers, the effective resistivity of insulators decreased as a function of linewidth, particularly for lines less than 10 /spl mu/m wide. However, even for narrow lines patterned in the top YBCO layer, critical current densities, J/sub c/(77 K), exceeded 106 A/cm/sup 2/.<>