Title :
A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications
Author :
Huang, Yuan-Hao ; Ma, Hsi-Pin ; Liou, Ming-Luen ; Chiueh, Tzi-Dar
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This work proposes a communication digital signal processor (DSP) suitable for massive signal processing operations in orthogonal frequency division multiplexing (OFDM) and code-division multiple-access (CDMA) communication systems. The OFDM-based IEEE 802.11a wireless LAN transceiver and CDMA-based WCDMA uplink receiver are simulated to evaluate the computation requirements of future communication systems. The architecture of the communication digital signal processor is established according to the computational complexity of these simulations. The proposed architecture supports basic butterfly operations, single/double-precision and real- and complex-valued multiplication-and-accumulation (MAC), squared error computation, and add-compare-select (ACS) operation. This butterfly/complex MAC architecture can greatly enhance the execution efficiency of operations often found in communication applications. The processor chip is fabricated using a 0.35-μm n-well one-poly four-metal CMOS technology. The fabricated DSP chip reaches a speed of 1.1 G MAC/s when operating in the high-speed mode, and it achieves 4 M MAC/s/mW in the low-power mode.
Keywords :
CMOS digital integrated circuits; code division multiple access; computational complexity; digital signal processing chips; frequency division multiple access; high-speed integrated circuits; transceivers; wireless LAN; 0.35 micron; CDMA communication systems; CDMA-based WCDMA uplink receiver; DSP chip; MAC architecture; OFDM; OFDM-based IEEE 802.11a wireless LAN transceiver; add-compare-select operation; butterfly operations; code-division multiple-access; complex-valued multiplication-and-accumulation; computation requirements; computational complexity; execution efficiency; future communication systems; high-speed mode; low-power mode; n-well one-poly four-metal CMOS technology; orthogonal frequency division multiplexing; processor chip; real-valued multiplication-and-accumulation; signal processing; single/double-precision; squared error computation; sub-word-parallel digital signal processor; wireless communication applications; CMOS technology; Computational modeling; Computer architecture; Digital signal processing; Digital signal processors; Multiaccess communication; OFDM; Transceivers; Wireless LAN; Wireless communication;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2003.820861