Challenges in the Cell-Based Design of Very-High-Speed SiGe-Bipolar ICs at 100 Gb/s

Author

Möller, Michael

Author_Institution

Dept. of Electron. & Circuits, Saarland Univ., Saarbrucken

Volume

43

Issue

9

fYear

2008

Firstpage

1877

Lastpage

1888

Abstract

A cell-based design concept for the efficient design of higher integrated SiGe-bipolar circuits operating at data rates equal to or greater than 100 Gb/s is proposed. The performance limitations of circuit designs at these high data rates are discussed with special regard to associated cell-based design aspects. The performances of two cell-based designs are demonstrated by a 100 Gb/s 2:1 multiplexer IC and a 100 Gb/s 1:2 demultiplexer IC with on-chip clock- and data-recovery.

Keywords

Ge-Si alloys; bipolar digital integrated circuits; demultiplexing equipment; integrated circuit design; multiplexing equipment; very high speed integrated circuits; SiGe; bit rate 100 Gbit/s; cell-based design; demultiplexer IC; multiplexer IC; on-chip clock and data recovery; very-high-speed bipolar IC; Bipolar transistor circuits; Circuit synthesis; Clocks; Cutoff frequency; Frequency conversion; Germanium silicon alloys; III-V semiconductor materials; Impedance; Multiplexing; Silicon germanium; 100 Gb/s cell-based design; Demultiplexer DEMUX; MUX; SiGe bipolar technology; dynamic offset; high- speed ICs; high-speed interfaces; impedance mismatch; modal effects; multiplexer;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2008.2002334

Filename

4625987