DocumentCode :
864089
Title :
Deterministic logic BIST for transition fault testing
Author :
Gherman, V. ; Wunderlich, H.-J. ; Schloeffel, J. ; Garbers, M.
Author_Institution :
CEA, Gif-sur-Yvette
Volume :
1
Issue :
3
fYear :
2007
fDate :
5/1/2007 12:00:00 AM
Firstpage :
180
Lastpage :
186
Abstract :
Built-in self-test (BIST) is an attractive approach to detect delay faults because of its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique that has been successfully applied to stuck-at fault testing. As delay faults have lower random pattern testability than stuck-at faults, the need for DLBIST schemes has increased. However, an extension to delay fault testing is not trivial as this necessitates the application of pattern pairs. As a consequence, delay fault testing is expected to require a larger mapping effort and logic overhead than stuck-at fault testing. With this in mind, the authors consider the so-called transition fault model, which is widely used for complexity reasons, and an extension of a DLBIST scheme for transition fault testing is presented. Functional justification is used to generate the required pattern pairs. The efficiency of the extended scheme is investigated using difficult-to-test industrial designs
Keywords :
built-in self test; fault diagnosis; logic testing; built-in self-test; delay fault detection; deterministic logic BIST; random pattern testability; stuck-at fault testing; transition fault testing;
fLanguage :
English
Journal_Title :
Computers & Digital Techniques, IET
Publisher :
iet
ISSN :
1751-8601
Type :
jour
Filename :
4205033
Link To Document :
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