Title :
Optimization of NbN MVTL logic gates for 10 K operation
Author :
Leung, M. ; Durand, D.J. ; Abelson, L.A. ; Eaton, L.R. ; Spargo, J.W.
Author_Institution :
TRW Inc., Redondo Beach, CA, USA
fDate :
6/1/1995 12:00:00 AM
Abstract :
We have systematically studies designs for Modified Variable Threshold Logic Gates (MVTL) in NbN within the framework of factorial analysis. Our goal is to attain optimized margin and fanout for 10 K operation. Significant parasitic inductances, associated with current crowding at junction vias, were measured and are found to affect the operating margin. We report the progression of designs, margin measurements and yield data for our 10 K circuits.<>
Keywords :
circuit optimisation; logic gates; niobium compounds; superconducting logic circuits; threshold logic; 10 K; NbN; NbN MVTL logic gates; current crowding; design; factorial analysis; fanout; junction vias; margin; modified variable threshold logic; optimization; parasitic inductances; yield; Coupling circuits; Critical current; Digital circuits; Inductance; Integrated circuit measurements; Logic design; Logic gates; Niobium; Proximity effect; SQUIDs;
Journal_Title :
Applied Superconductivity, IEEE Transactions on
