A device model investigation of power Si/GaP heterojunction gate turn-off thyristors

A device model investigation is made of power Si/GaP heterojunction gate-turn-off thyristors (GTOs), making use of previously published modeling tools, i.e. a one-dimensional model for GaAs/AlAs HBTs with a change in physical constants and a circuit simulator that allows the direct embedding of the one-dimensional model in an arbitrary circuit. By means of these modeling tools, design optimization is carried out for both homojunction and heterojunction GTOs. Comparison under the condition of an identical on-state voltage shows that the best heteroepitaxial GTO with an n-buffer layer exhibits an improvement in turn-off loss of a factor of 1.55 over the best homoepitaxial GTO of the same structure. This factor becomes 1.86 if a slight increase in the on-state voltage is permitted