A Top-Down Approach to Architecting CPI Component Performance Counters

Software developers can gain insight into software-hardware interactions by decomposing processor performance into individual cycles-per-instruction components that differentiate cycles consumed in active computation from those spent handling various miss events. Constructing accurate CPI components for out-of-order superscalar processors is complicated, however, because computation and miss event handling overlap. The authors´ counter architecture, using an analytical superscalar performance model, handles overlap effects more accurately than existing methods