• DocumentCode
    865268
  • Title

    Steady-state error minimisation technique for single-phase PWM inverters

  • Author

    Chung, Se-Kyo

  • Author_Institution
    Dept. of Control & Instrum. Eng., Gyeongsang Nat. Univ., Kyungnam, South Korea
  • Volume
    38
  • Issue
    22
  • fYear
    2002
  • fDate
    10/24/2002 12:00:00 AM
  • Firstpage
    1378
  • Lastpage
    1380
  • Abstract
    A steady-state error minimisation technique of a single-phase pulsewidth modulated (PWM) inverter is presented. This technique employs a phase-locked loop concept utilising the phase difference between the capacitor voltage and current, which is similar to the dq transform of three phase variables. The experimental results are provided to show the effectiveness of this approach.
  • Keywords
    DC-AC power convertors; PWM invertors; errors; minimisation; capacitor current; capacitor voltage; dq transform; phase difference; phase-locked loop concept; single-phase PWM inverters; steady-state error minimisation technique; three phase variables;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20020908
  • Filename
    1047110
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=865268