• DocumentCode
    86561
  • Title

    Multi-Channel Architecture-Based FTL for Reliable and High-Performance SSD

  • Author

    Jen-Wei Hsieh ; Han-Yi Lin ; Dong-Lin Yang

  • Author_Institution
    Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan
  • Volume
    63
  • Issue
    12
  • fYear
    2014
  • fDate
    Dec. 2014
  • Firstpage
    3079
  • Lastpage
    3091
  • Abstract
    Several excellent researches have been proposed to improve the performance of solid-state drives (SSDs) by exploiting I/O parallelism of multi-channel architecture. However, these researches do not fully explore the internal parallelism and do not take wear leveling into consideration. In this paper, I/O performance is further improved by interleaving requests in channel level and striping sub-requests in plane level. A wear-leveling-aware distributed garbage collector is proposed to improve SSD lifetime and reclamation efficiency. To balance the utilization of user space among all channels, data migration is performed implicitly during channel selection and explicitly during garbage collection. To the best of our knowledge, this is the first paper on the design of distributed garbage collector for multi-channel flash-memory storage system. The experimental results showed that the proposed scheme can achieve good wear leveling and improve the overall performance by 34% for the Windows workload, 56.5% for the Linux workload, 88.4% for the multimedia workload, and 9.3% for the on-line transaction processing (OLTP) workload under the two-die-two-plane architecture, compared with the related work.
  • Keywords
    flash memories; IO parallelism; OLTP; SSD lifetime; SSD reclamation efficiency; channel level; channel selection; high-performance SSD; interleaving requests; multichannel architecture; multichannel architecture-based FTL; multichannel flash-memory storage system; on-line transaction processing workload; plane level; reliable SSD; solid-state drives; striping subrequests; two-die-two-plane architecture; wear-leveling-aware distributed garbage collector; Computer architecture; Microprocessors; Parallel processing; Solid state circuits; Throughput; Solid-state drive (SSD); distributed garbage collector; external parallelism; internal parallelism; wear leveling;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2013.169
  • Filename
    6582411