• DocumentCode
    865983
  • Title

    High-speed, low-complexity systolic designs of novel iterative division algorithms in GF(2m)

  • Author

    Wu, Chien-Hsing ; Wu, Chien-Ming ; Shieh, Ming-Der ; Hwang, Yin-Tsung

  • Author_Institution
    Electr. Eng. Dept., Nat. Chung-Cheng Univ., Ming-Hsiung, Taiwan
  • Volume
    53
  • Issue
    3
  • fYear
    2004
  • fDate
    3/1/2004 12:00:00 AM
  • Firstpage
    375
  • Lastpage
    380
  • Abstract
    We extend the binary algorithm invented by Stein and propose novel iterative division algorithms over GF(2m) for systolic VLSI realization. While algorithm EBg is a basic prototype with guaranteed convergence in at most 2m - 1 iterations, its variants, algorithms EBd and EBdf, are designed for reduced complexity and fixed critical path delay, respectively. We show that algorithms EBd and EBdf can be mapped to parallel-in parallel-out systolic circuits with low area-time complexities of O(m2loglogm) and O(m2), respectively. Compared to the systolic designs based on the extended Euclid´s algorithm, our circuits exhibit significant speed and area advantages.
  • Keywords
    Galois fields; VLSI; circuit complexity; digital arithmetic; systolic arrays; Euclid algorithm; algorithm EBd; algorithm EBdf; algorithm EBg; binary algorithm; circuit complexity; finite field; iterative division algorithm; systolic VLSI design; Algorithm design and analysis; Arithmetic; Circuits; Convergence; Delay; Equations; Iterative algorithms; Prototypes; Public key cryptography; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2004.1261843
  • Filename
    1261843