Title :
Low-power design using multiple channel lengths and oxide thicknesses
Author :
Sirisantana, Naran ; Roy, Kaushik
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
Two CMOS design techniques use dual threshold voltages to reduce power consumption while maintaining high performance. Simulation results show power savings of 21% for one technique at low activity, and for the other, 19% at high activity and 38% at tow activity.
Keywords :
CMOS digital integrated circuits; electronic engineering computing; integrated circuit design; low-power electronics; CMOS design techniques; CMOS digital circuits; dual threshold voltages; electronic engineering computing; power consumption; CMOS technology; Capacitance; Doping; Energy consumption; Impurities; Leakage current; MOSFETs; Subthreshold current; Threshold voltage; Tunneling;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2004.1261850
