Architecture for motion estimation using the one-dimensional hierarchical search block-matching algorithm

The realisation of a real-time video-coding system calls for a dedicated motion-estimation architecture. Whereas all the existing motion-estimation architectures offer either computational speed or hardware simplicity, in this paper, the authors propose an efficient pipelined parallel architecture for the one-dimensional hierarchical search (1DHS) block-matching algorithm that is efficient in terms of both speed and hardware cost. The architecture exploits the advantageous features of the 1DHS algorithm and makes use of an intelligent memory configuration to achieve high speed while keeping the hardware complexity low. The architecture also makes use of a data-reuse technique, thereby reducing the number of external memory accesses. The proposed architecture has been modelled in VHDL and simulated to establish its functional validity.