Title :
Estimating the complexity of synthesized designs from FSM specifications
Author :
Mitra, Biswadip ; Panda, Preeti Ranjan ; Chaudhuri, P. Pal
Author_Institution :
Texas Instruments, Bangalore, India
fDate :
3/1/1993 12:00:00 AM
Abstract :
A procedure for estimating the complexity of synthesized designs from finite-state machine (FSM) specifications is described. Incorporating this estimate in the data path synthesis stage allows a trade-off between data path and control logic, resulting in high quality designs in terms of synthesized logic area. It is shown that the estimation process takes 650 to 3000 times less CPU time than the synthesis procedure.<>
Keywords :
computational complexity; finite state machines; formal specification; logic design; complexity estimation; control logic; data path synthesis; finite state machine specifications; synthesized designs; Algorithm design and analysis; Central Processing Unit; Cost function; High level synthesis; Instruments; Libraries; Logic design; Optimal control; Scheduling algorithm; Stochastic processes;
Journal_Title :
Design & Test of Computers, IEEE
