• DocumentCode
    866524
  • Title

    A methodology for synthesis of data path circuits

  • Author

    Chowdhary, Amit ; Gupta, Rajesh K.

  • Author_Institution
    Design Technol. Div., Intel Corp., Santa Clara, CA, USA
  • Volume
    19
  • Issue
    6
  • fYear
    2002
  • Firstpage
    90
  • Lastpage
    100
  • Abstract
    This methodology extracts the regularity of data path blocks from their HDL descriptions and preserves it throughout the synthesis process. By automating various design steps, the methodology significantly improves design productivity and achieves designs comparable in terms of delay and size to manually designed circuits.
  • Keywords
    hardware description languages; logic CAD; HDL descriptions; automated design steps; data path block regularity; data path circuit synthesis methodology; delay; design productivity; size; Adders; Arithmetic; Circuit synthesis; Data mining; Design methodology; Hardware design languages; Libraries; Logic design; Process design; Productivity;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2002.1047748
  • Filename
    1047748
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=866524