Title :
Bit-error-rate performance of intra-chip wireless interconnect systems
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
Abstract :
This Letter evaluates the bit-error rate (BER) performance of a coherent binary phase-shift keying interconnect system operating on an intra-chip wireless channel at 15 GHz. Results show that the system performance degrades with the separation distance and the data rate. A high data rate at 2 Gb/s with a low BER<10-5 over the entire chip of size 20 × 20 mm can be achieved with the transmitted power of 10 dBm.
Keywords :
error statistics; interconnected systems; phase shift keying; radio links; 15 GHz; 2 Gbits/s; 20 mm; BER; BPSK; bit-error-rate performance; chip size; chip-scale wireless communications system; coherent binary phase-shift keying interconnect system; data rate; intra-chip wireless channel; system performance; transmitted power; Binary phase shift keying; Bit error rate; Clocks; Communication switching; Integrated circuit interconnections; Phase shift keying; Power system interconnection; Receiving antennas; Rician channels; Transmitting antennas;
Journal_Title :
Communications Letters, IEEE
DOI :
10.1109/LCOMM.2003.822514
