Title :
A data-reuse architecture for gray-scale morphologic operations
Author :
Sheu, Ming-hwa ; Wang, Jhing-Fa ; Chen, Jer-Sheng ; Suen, An-Nan ; Jeang, Yuan-Long ; Lee, Jau-Yien
Author_Institution :
Nat. Cheng Kung Univ., Tainan, Taiwan
fDate :
10/1/1992 12:00:00 AM
Abstract :
Presents an efficient pipeline architecture to perform gray-scale morphologic operations. The features of the architecture are 1) lower hardware cost, 2) faster operation time in processing an image, 3) lower data access times from the image memory, 4) shorter latency, 5) suitability for VLSI implementation, and 6) adaptability for N×N morphologic operations
Keywords :
VLSI; image processing; parallel architectures; pipeline processing; VLSI implementation; adaptability; data access times; data-reuse architecture; gray-scale morphologic operations; image memory; image processing; latency; operation time; pipeline architecture; Costs; Delay; Electrons; Gray-scale; Hardware; Image analysis; Morphology; Pipelines; Pixel; Very large scale integration;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
