A clock distribution scheme for large RSFQ circuits

A primary issue in maximizing the performance of large scale synchronous digital systems is the clock distribution scheme. We present novel clocking scheme, developed specifically for RSFQ logic, which is based on the concurrent flow of the clock and data signals. The scheme permits the circuit throughput to be independent of inter-cell connection delays and significantly reduces the dependence of the throughput on the clock-to-output delay of the cells. Concurrent flow clocking is particularly well for structured architectures. The simulated maximum clock frequency of an RSFQ decimation digital filter currently under development at the University of Rochester can be as much as seven times higher using concurrent-flow clocking rather than conventional (counterflow) clocking. This advantage, however, is reduced to a factor of two due to fabrication parameter variations in present day superconductive technologies.<>