Title :
A hardware accelerator for maze routing
Author :
Won, Youngju ; Sahni, Sartaj ; El-Ziq, Yacoub
Author_Institution :
Gongneung Nowo-Gu, Seoul, South Korea
fDate :
1/1/1990 12:00:00 AM
Abstract :
A hardware accelerator for the maze routing problem is developed. This accelerator consists of three three-stage pipelines. Banked memory is used to avoid memory read/write conflicts and obtain maximum efficiency. The design is compared to other proposed designs. Unlike other proposed hardware solutions for this problem, this design does not require an increase in the number of processors as the problem size increases
Keywords :
circuit layout CAD; banked memory; hardware accelerator; maze routing; three-stage pipelines; Broadcasting; Computer science; Electron accelerators; Hardware; Logic; Pipelines; Routing;
Journal_Title :
Computers, IEEE Transactions on
