A Multiprocessor Bus Architecture for the LEP Control System

The architecture and the system aspects of the multi-master bus used for the construction of the process computer assemblies and the message handling assemblies of the LEP control system are presented. This bus architecture provides a fully distributed reservation mechanism and a protected access of the peripherals to prevent processor interferences. To achieve this, a channel concept is proposed, using a system bus for communication between processors and with their peripherals. The architecture is microprocessor independent, provides dynamic bus allocation amongst several microcomputers, offers processor position independence and has a multimaster bus extension to several crates with a homogeneous addressing. A global system concept, called E3S, has been developed including the definition of software primitives. The bus access software is organised in a layered structure matching the module functionality.