A reduced common mode hysteresis current regulation strategy for multilevel inverters

This paper presents a new hysteresis current regulation technique with reduced common mode switching for three-phase multilevel inverters. The proposed technique uses three independent multilevel hysteresis current regulators to generate three sets of complementary gating signals through the comparison of the measured current errors with implemented hysteresis limits. These gating signals are then distributed to each complementary switch pair of the multilevel inverter structure to switch with reduced common mode voltage. Additionally, by intelligently compensating for transition delays during dead-times, common mode voltage can essentially be eliminated completely. Two versions of the common mode regulation technique are derived by using either the line currents or differences between the line currents, known as delta currents, as the control variables. A detailed investigation is presented to determine that the delta currents are the optimal control variables. The performance of the proposed strategy is confirmed through both simulation and experimental investigations.