DocumentCode :
86853
Title :
Analysis and Experimental Study of the Package Stresses in a QFN Plastic-Encapsulated Package
Author :
Jiyuan Luan ; Blackie, Campbell
Author_Institution :
Texas Instrum. Inc., Santa Clara, CA, USA
Volume :
4
Issue :
8
fYear :
2014
fDate :
Aug. 2014
Firstpage :
1303
Lastpage :
1308
Abstract :
Plastic-encapsulated packages are known to suffer package stress issues which often cause undesired shifts in the IC electrical parameters. Two types of package stress are analyzed and their contributions to the overall package stress in a Quad-Flat No-leads (QFN) Package are experimentally studied in this paper. The volumetric package stress generated by the mold compound is analyzed using the material properties of the bulk modulus and the volumetric coefficient of thermal expansion (vCTE). The in-plane package stress generated by the die and the die-attach material is analyzed using the structural analysis method with the introduction of an improved Suhir solution to evaluate the in-plane normal stress at the active area of the IC die. These theoretical analysis results are further experimentally studied with the functional measurements on a precision CMOS bandgap voltage reference in a QFN package. Using the combination of two different die-attach methods and two different die-coating conditions, the parametric variations in the bandgap voltage can be correlated with the different types of package stress. The actual test data presented in this paper are in good agreement with the theoretical analysis results.
Keywords :
CMOS integrated circuits; coatings; encapsulation; integrated circuit packaging; microassembling; stress analysis; IC die; IC electrical parameters; QFN plastic-encapsulated package; bandgap voltage; bulk modulus; die-attach material; die-attach methods; die-coating conditions; improved Suhir solution; in-plane normal stress; in-plane package stress; material properties; mold compound; package stress analysis; parametric variations; precision CMOS bandgap voltage reference; quad-flat no-leads package; structural analysis method; test data; vCTE; volumetric coefficient of thermal expansion; volumetric package stress; Accuracy; Integrated circuits; Packaging; Photonic band gap; Silicon; Stress; In-plane package stress; microelectronics packaging; package stress; structural analysis method; volumetric package stress; volumetric package stress.;
fLanguage :
English
Journal_Title :
Components, Packaging and Manufacturing Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
2156-3950
Type :
jour
DOI :
10.1109/TCPMT.2014.2330856
Filename :
6851172
Link To Document :
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