DocumentCode :
868950
Title :
A 0.5 MHz-0.9 MHz single-chip NMOS PLL LSI for frequency synthesizer
Author :
Yamase, Shinya ; Ando, Ryoichi ; Kimura, Kazuhiro ; Ozawa, Toshiyuki ; Dasai, Fumihiro
Author_Institution :
Sanyo Electr. Co. Ltd., Gunma, Japan
Volume :
34
Issue :
3
fYear :
1988
fDate :
8/1/1988 12:00:00 AM
Firstpage :
660
Lastpage :
666
Abstract :
A phase-locked loop (PLL) large-scale integration (LSI) chip operating in the broadcast frequency band from MF to UHF has been developed using an N-channel enhanced double diffusion (ED) MOS process technology with 0.8- mu m effective channel length. The operation of the PLL has been verified for frequencies from 0.2 MHz to 1200 MHz for a power-supply voltage of 5 V and an input signal amplitude of 100 mV RMS. The authors describe the N-channel ED MOS process technology that enables direct division of high-frequency signals up to the UHF band, and the high-speed circuit technology, functions, and special features of the circuit.
Keywords :
MOS integrated circuits; frequency synthesizers; large scale integration; phase-locked loops; 0.2 to 1200 MHz; 0.8 micron; 100 mV; 5 V; HF; MF; MOS process technology; N-channel enhanced double diffusion; UHF; VHF; audio system; broadcast frequency band; chip; frequency synthesizer; high-speed circuit technology; large-scale integration; phase-locked loop; single-chip NMOS PLL LSI; Broadcast technology; Broadcasting; Circuits; Frequency synthesizers; Geometry; Implants; Large scale integration; MOS devices; Phase locked loops; Power supplies; Propagation delay; Signal processing; UHF circuits; Voltage;
fLanguage :
English
Journal_Title :
Consumer Electronics, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-3063
Type :
jour
DOI :
10.1109/30.20167
Filename :
20167
Link To Document :
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