A 40-GHz Flip-Flop-Based Frequency Divider

Author

Heydari, Payam ; Mohanavelu, Ravindran

Author_Institution

Electron. Eng. & Comput. Sci., California Univ., Irvine, CA

Volume

53

Issue

12

fYear

2006

Firstpage

1358

Lastpage

1362

Abstract

This brief presents the design and implementation of a 40-GHz flip-flop-based frequency divider which incorporates a novel latch topology with two distinct tail current sources and an enabled cross-coupled pair during the tracking mode. The proposed topology will speed up the latch operation and increase the driving capability. It is capable of performing frequency division at 40 GHz without shunt or series peaking inductors. The circuit was fabricated in a 0.18-mum SiGe BiCMOS process, where only CMOS transistors were used. It draws an average current of 5 mA from a 1.8-V supply voltage

Keywords

BiCMOS integrated circuits; Ge-Si alloys; flip-flops; frequency dividers; transceivers; 0.18 micron; 1.8 V; 40 GHz; BiCMOS; SiGe; cross coupled pair; current mode logic; flip flop; frequency divider; latch topology; tail current sources; wireline transceiver; BiCMOS integrated circuits; CMOS process; Circuit topology; Frequency conversion; Germanium silicon alloys; Inductors; Latches; Shunt (electrical); Silicon germanium; Tail; Current-mode logic (CML); frequency divider (FD); high speed; latch; wireline transceiver;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2006.885393

Filename

4033149