DocumentCode
869406
Title
All-Digital Fast-Locked Synchronous Duty-Cycle Corrector
Author
Kao, Shao-Ku ; Liu, Shen-Iuan
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
Volume
53
Issue
12
fYear
2006
Firstpage
1363
Lastpage
1367
Abstract
An all-digital fast-locked synchronous duty-cycle corrector is presented. It corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The proposed circuit has been fabricated in a 0.18-mum CMOS technology. The measured duty-cycle error is between 1.5% and -1.4% for the input duty cycle of 40%~60%. The measured peak-to-peak jitter is 12.9ps at 1GHz. The measured operation frequency range is from 0.8GHz to 1.2 GHz
Keywords
CMOS integrated circuits; clocks; jitter; 0.18 micron; 0.8 to 1.2 GHz; 1 GHz; 12.9 ps; CMOS technology; all digital; duty cycle error; fast locked; input clock; output clock; peak to peak jitter; synchronous duty cycle corrector; CMOS technology; Circuits; Clocks; Delay lines; Feedback; Frequency synchronization; Interpolation; Phase locked loops; Pulse measurements; Space vector pulse width modulation; All-digital; duty-cycle corrector (DCC); fast- locked;
fLanguage
English
Journal_Title
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher
ieee
ISSN
1549-7747
Type
jour
DOI
10.1109/TCSII.2006.885396
Filename
4033152
Link To Document