Drain-induced barrier lowering in buried-channel MOSFET´s

Author

Van der Tol, Michael J. ; Chamberlain, Savvas G.

Author_Institution

Dept. of Electr. Eng., Waterloo Univ., Ont., Canada

Volume

40

Issue

4

fYear

1993

fDate

4/1/1993 12:00:00 AM

Firstpage

741

Lastpage

749

Abstract

In the literature, it is unclear whether or not buried-channel (BC) MOSFETs are less resistant to drain-induced barrier lowering than surface-channel MOSFETs. The authors clarify this confusion and experimentally demonstrate the relationship between the threshold voltage and channel length reduction for normally-on (inverting) BC-MOSFETs. The results are compared with similar measurements on surface-channel MOSFETs. It is shown that BC-MOSFETs are more prone to drain-induced barrier lowering than surface-channel MOSFETs. A simple analytic model is derived for the subthreshold current in small-geometry BC-MOSFETs. The model shows good agreement with experimental measurements and with subthreshold currents obtained using a two-dimensional numerical simulator

Keywords

insulated gate field effect transistors; semiconductor device models; BC-MOSFETs; analytic model; buried channel MOSFETs; channel length reduction; drain-induced barrier lowering; experimental measurements; normally on MOSFETs; subthreshold current; surface-channel MOSFETs; threshold voltage; two-dimensional numerical simulator; Analytical models; Councils; Electrons; MOSFET circuits; Numerical simulation; Resistance; Scholarships; Subthreshold current; Threshold voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.202786

Filename

202786