Title :
An analytical back-gate bias effect model for ultrathin SOI CMOS devices
Author :
Sim, Jai-hoon ; Kuo, James B.
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
4/1/1993 12:00:00 AM
Abstract :
An analytical back-gate bias effect model for ultrathin SOI CMOS devices is presented. As verified by PISCES results, the analytical SOI CMOS back-gate bias effect model provides a much better accuracy in the integral potential distribution and the threshold voltage as the back-gate bias is changed
Keywords :
CMOS integrated circuits; semiconductor device models; semiconductor-insulator boundaries; PISCES results; analytical model; back-gate bias effect model; integral potential distribution; threshold voltage; ultrathin SOI CMOS devices; Capacitance; Electrostatics; Insulation; MOS devices; Semiconductor device modeling; Semiconductor films; Silicon; Substrates; Thin film devices; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
